20 search results - page 3 / 4 » Logical Verification of the NVAX CPU Chip Design |
FPGA
2004
ACM
13 years 10 months ago
2004
ACM
This paper shows a method to verifying the thermal status of complex FPGA-based circuits like microprocessors. Thus, the designer can evaluate if a particular block is working bey...
DAC
2010
ACM
13 years 9 months ago
2010
ACM
Timing exception verification has become a center of interest as incorrect constraints can lead to chip failures. Proving that a false path is valid or not is a difficult problem ...
DAC
2001
ACM
14 years 6 months ago
2001
ACM
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
DAC
1994
ACM
13 years 9 months ago
1994
ACM
Today's high-performance single-chip CMOS microprocessors are the most complex and challenging chip designs ever implemented. To stay on the leading edge, Digital's micro...
ICCD
2003
IEEE
14 years 2 months ago
2003
IEEE
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...