35 search results - page 3 / 7 » Loop Scheduling and Partitions for Hiding Memory Latencies |
CASES
2004
ACM
13 years 10 months ago
2004
ACM
A coarse-grain multithreaded processor can effectively hide long memory latencies by quickly switching to an alternate task when the active task issues a memory request, improving...
ICCAD
2009
IEEE
13 years 3 months ago
2009
IEEE
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
HPCA
1999
IEEE
13 years 9 months ago
1999
IEEE
This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/ execute decoupling and simultaneous multithreading. We investigate how b...
ASPDAC
2012
ACM
12 years 29 days ago
2012
ACM
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
ISCA
2011
IEEE
12 years 9 months ago
2011
IEEE
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...