5 search results - page 1 / 1 » Loop Scheduling with Complete Memory Latency Hiding on Multi... |
ICPADS
2006
IEEE
13 years 10 months ago
2006
IEEE
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
TECS
2010
13 years 3 months ago
2010
MICRO
2000
IEEE
13 years 4 months ago
2000
IEEE
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
PLDI
1995
ACM
13 years 8 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
MICRO
1997
IEEE
13 years 9 months ago
1997
IEEE
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...