Sciweavers

20 search results - page 4 / 4
» Loop Selection for Thread-Level Speculation
Sort
View
MICRO
1996
IEEE
97views Hardware» more  MICRO 1996»
13 years 9 months ago
Modulo Scheduling of Loops in Control-intensive Non-numeric Programs
Much of the previous work on modulo scheduling has targeted numeric programs, in which, often, the majority of the loops are well-behaved loop-counter-based loops without early ex...
Daniel M. Lavery, Wen-mei W. Hwu
HPCA
2004
IEEE
14 years 5 months ago
Understanding Scheduling Replay Schemes
Modern microprocessors adopt speculative scheduling techniques where instructions are scheduled several clock cycles before they actually execute. Due to this scheduling delay, sc...
Ilhyun Kim, Mikko H. Lipasti
IPPS
2009
IEEE
13 years 11 months ago
Accelerating HMMer on FPGAs using systolic array based architecture
HMMer is a widely-used bioinformatics software package that uses profile HMMs (Hidden Markov Models) to model the primary structure consensus of a family of protein or nucleic aci...
Yanteng Sun, Peng Li, Guochang Gu, Yuan Wen, Yuan ...
MICRO
1998
IEEE
139views Hardware» more  MICRO 1998»
13 years 9 months ago
A Dynamic Multithreading Processor
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
Haitham Akkary, Michael A. Driscoll
CJ
2006
84views more  CJ 2006»
13 years 4 months ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope