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VTS
2005
IEEE
89views Hardware» more  VTS 2005»
13 years 11 months ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
CHES
2004
Springer
170views Cryptology» more  CHES 2004»
13 years 10 months ago
Concurrent Error Detection Schemes for Involution Ciphers
Because of the rapidly shrinking dimensions in VLSI, transient and permanent faults arise and will continue to occur in the near future in increasing numbers. Since cryptographic c...
Nikhil Joshi, Kaijie Wu, Ramesh Karri
DSD
2010
IEEE
111views Hardware» more  DSD 2010»
13 years 3 months ago
Faults Coverage Improvement Based on Fault Simulation and Partial Duplication
— A method how to improve the coverage of single faults in combinational circuits is proposed. The method is based on Concurrent Error Detection, but uses a fault simulation to f...
Jaroslav Borecky, Martin Kohlik, Hana Kubatova, Pa...
VTS
1999
IEEE
125views Hardware» more  VTS 1999»
13 years 9 months ago
Error Detecting Refreshment for Embedded DRAMs
This paper presents a new technique for on-line consistency checking of embedded DRAMs. The basic idea is to use the periodic refresh operation for concurrently computing a test c...
Sybille Hellebrand, Hans-Joachim Wunderlich, Alexa...
ICMCS
2006
IEEE
105views Multimedia» more  ICMCS 2006»
13 years 11 months ago
Embedded Convolutional Face Finder
In this paper, a high-level optimization methodology is applied for the implementation of the well-known Convolutional Face Finder (CFF) algorithm for real-time applications on ce...
Sébastien Roux, Franck Mamalet, Christophe ...