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IAJIT
2010
107views more  IAJIT 2010»
13 years 3 months ago
Low Latency, High Throughput, and Less Complex VLSI Architecture for 2D-DFT
: This paper proposes a pipelined, systolic architecture for two- dimensional discrete Fourier transform computation which is highly concurrent. The architecture consists of two, o...
Sohil Shah, Preethi Venkatesan, Deepa Sundar, Muni...
ICIP
2003
IEEE
14 years 6 months ago
Parallel-pipelined architecture for 2-D ICT VLSI implementation
The Integer Cosine Transform (ICT) has been shown to be an alternative to the DCT for image processing. This paper presents a parallel-pipelined architecture of an 8x8 ICT(10, 9, ...
Juan A. Michell, Gustavo A. Ruiz, Angel M. Buron
IPPS
1998
IEEE
13 years 9 months ago
HIPIQS: A High-Performance Switch Architecture Using Input Queuing
Switch-based interconnects are used in a number of application domains including parallel system interconnects, local area networks, and wide area networks. However, very few swit...
Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. P...
IPPS
2007
IEEE
13 years 11 months ago
Speculative Flow Control for High-Radix Datacenter Interconnect Routers
High-radix switches are desirable building blocks for large computer interconnection networks, because they are more suitable to convert chip I/O bandwidth into low latency and lo...
Cyriel Minkenberg, Mitchell Gusat
CCR
2006
122views more  CCR 2006»
13 years 5 months ago
Low complexity, stable scheduling algorithms for networks of input queued switches with no or very low speed-up
The delay and throughput characteristics of a packet switch depend mainly on the queueing scheme and the scheduling algorithm deployed at the switch. Early research on scheduling ...
Claus Bauer