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ICCD
2005
IEEE
159views Hardware» more  ICCD 2005»
13 years 10 months ago
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
ICPADS
2002
IEEE
13 years 9 months ago
Self-Stabilizing Wormhole Routing on Ring Networks
Wormhole routing is most common in parallel architectures in which messages are sent in small fragments called flits. It is a lightweight and efficient method of routing message...
Ajoy Kumar Datta, Maria Gradinariu, Anthony B. Ken...
ISCA
2012
IEEE
320views Hardware» more  ISCA 2012»
11 years 7 months ago
Viper: Virtual pipelines for enhanced reliability
The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device rel...
Andrea Pellegrini, Joseph L. Greathouse, Valeria B...
ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
13 years 11 months ago
Dynamic prediction of architectural vulnerability from microarchitectural state
Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. ...
Kristen R. Walcott, Greg Humphreys, Sudhanva Gurum...
EDCC
2006
Springer
13 years 8 months ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...