15 search results - page 1 / 3 » Low Power Bus Encoding Technique Considering Coupling Effect... |
IMECS
2007
13 years 6 months ago
2007
— In this paper, we propose a bus encoding scheme to minimize coupling effects which cause significant power consumption in the on-chip interconnects. The proposed bus encoding s...
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is proposed t...
DAC
2001
ACM
14 years 5 months ago
2001
ACM
Due to larger buses (length, width) and deep sub-micron effects where coupling capacitances between bus lines are in the same order of magnitude as base capacitances, power consum...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
In this paper, we propose an adaptive low-power bus encoding algorithm based on weighted code mapping (WCM) and the delayed bus technique. The WCM algorithm transforms an original...
CASES
2003
ACM
13 years 10 months ago
2003
ACM
Reducing the power consumption of computing devices has gained a lot of attention recently. Many research works have focused on reducing power consumption in the off-chip buses as...