11 search results - page 2 / 3 » Low power block based FIR filtering cores |
ISCAS
1999
IEEE
13 years 9 months ago
1999
IEEE
The authors present a multiplication algorithm for low power implementation of digital filters on CMOS based digital signal processing systems. The algorithm decomposes individual...
PATMOS
2007
Springer
13 years 11 months ago
2007
Springer
In this work we consider coefficient reordering for low power realization of FIR filters on fixed-point multiply-accumulate (MAC) based architectures, such as DSP processors. Com...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
The increasing demand for FPGAs and reconfigurable hardware targeting high performance low power applications has lead to an increasing requirement for new high performance reconf...
NOCS
2007
IEEE
13 years 11 months ago
2007
IEEE
Recent remarkable advances in nanoscale siliconphotonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the uni...
MVA
2007
13 years 6 months ago
2007
This paper describes a new, powerful technique of fingerprint verification based on a perturbation method. The proposed method consists of four parts. The first part performs loca...