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ISLPED
1997
ACM
99views Hardware» more  ISLPED 1997»
13 years 9 months ago
Low power data processing by elimination of redundant computations
We suggest a new technique to reduce energy consumption in the processor datapath without sacrificing performance by exploiting operand value locality at run time. Data locality is...
Mir Azam, Paul D. Franzon, Wentai Liu
DATE
2005
IEEE
140views Hardware» more  DATE 2005»
13 years 10 months ago
Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing
We present a novel, quality-driven, architectural-level approach that trades-off the output quality to enable power-aware processing of multimedia streams. The error tolerance of ...
Shrirang M. Yardi, Michael S. Hsiao, Thomas L. Mar...
LCTRTS
2007
Springer
13 years 11 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
TVLSI
2010
12 years 11 months ago
A Low-Power DSP for Wireless Communications
This paper proposes a low-power high-throughput digital signal processor (DSP) for baseband processing in wireless terminals. It builds on our earlier architecture--Signal processi...
Hyunseok Lee, Chaitali Chakrabarti, Trevor N. Mudg...
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
13 years 10 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...