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DAC
2003
ACM
14 years 6 months ago
A survey of techniques for energy efficient on-chip communication
Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems bei...
Vijay Raghunathan, Mani B. Srivastava, Rajesh K. G...
DAC
2005
ACM
14 years 6 months ago
System-level energy-efficient dynamic task scheduling
Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor energy by slowing down the DVS processor and stretching the task execution time...
Jianli Zhuo, Chaitali Chakrabarti
ICMCS
2005
IEEE
158views Multimedia» more  ICMCS 2005»
13 years 11 months ago
Processor Load Analysis for Mobile Multimedia Streaming: The Implication of Power Reduction
The software codec on mobile device introduces significant power consumption because the energy efficiency of general processor based system is much lower than that of the dedicat...
Min Li, Xiaobo Wu, Zihua Guo, Richard Yao, Xiaolan...
ISLPED
2007
ACM
123views Hardware» more  ISLPED 2007»
13 years 6 months ago
Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules
We address power minimization of earliest deadline first and ratemonotonic schedules by voltage and frequency scaling. We prove that the problems are NP-hard, and present (1+ ) f...
Sushu Zhang, Karam S. Chatha, Goran Konjevod
CASES
2004
ACM
13 years 10 months ago
Reducing both dynamic and leakage energy consumption for hard real-time systems
While the dynamic voltage scaling (DVS) techniques are efficient in reducing the dynamic energy consumption for the processor, varying voltage alone becomes less effective for t...
Linwei Niu, Gang Quan