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FMCAD
2004
Springer
13 years 10 months ago
Increasing the Robustness of Bounded Model Checking by Computing Lower Bounds on the Reachable States
Most symbolic model checkers are based on either Binary Decision Diagrams (BDDs), which may grow exponentially large, or Satisfiability (SAT) solvers, whose time requirements rapi...
Mohammad Awedh, Fabio Somenzi
EMSOFT
2009
Springer
13 years 8 months ago
Modular static scheduling of synchronous data-flow networks: an efficient symbolic representation
This paper addresses the question of producing modular sequential imperative code from synchronous data-flow networks. Precisely, given a system with several input and output flow...
Marc Pouzet, Pascal Raymond
ICCAD
2009
IEEE
161views Hardware» more  ICCAD 2009»
13 years 2 months ago
The epsilon-approximation to discrete VT assignment for leakage power minimization
As VLSI technology reaches 45nm technology node, leakage power optimization has become a major design challenge. Threshold voltage (vt) assignment has been extensively studied, du...
Yujia Feng, Shiyan Hu
DAC
2004
ACM
14 years 5 months ago
Fast statistical timing analysis handling arbitrary delay correlations
CT An efficient statistical timing analysis algorithm that can handle arbitrary (spatial and structural) causes of delay correlation is described. The algorithm derives the entire ...
Michael Orshansky, Arnab Bandyopadhyay