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» Lower bounds on power dissipation for DSP algorithms
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ISLPED
1996
ACM
72views Hardware» more  ISLPED 1996»
13 years 9 months ago
Simultaneous buffer and wire sizing for performance and power optimization
In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions...
Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
13 years 10 months ago
Security-Driven Exploration of Cryptography in DSP Cores
With the popularity of wireless communication devices a new important dimension of embedded systems design has arisen, that of security. This paper presents for the first time des...
Catherine H. Gebotys
ISSS
2000
IEEE
127views Hardware» more  ISSS 2000»
13 years 9 months ago
Lower Bound Estimation for Low Power High-Level Synthesis
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Sta...
FOCS
2008
IEEE
13 years 11 months ago
Lower Bounds for Noisy Wireless Networks using Sampling Algorithms
We show a tight lower bound of Ω(N log log N) on the number of transmissions required to compute several functions (including the parity function and the majority function) in a...
Chinmoy Dutta, Jaikumar Radhakrishnan
ICCAD
1997
IEEE
106views Hardware» more  ICCAD 1997»
13 years 9 months ago
Accurate power estimation for large sequential circuits
A power estimation approach is presented in which blocks of consecutive vectors are selected at random from a user-supplied realistic input vector set and the circuit is simulated...
Joseph N. Kozhaya, Farid N. Najm