18 search results - page 4 / 4 » Lowering Power Consumption in Clock by Using Globally Asynch... |
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architec...
PATMOS
2005
Springer
13 years 10 months ago
2005
Springer
Abstract. Based on a previously reported request driven technique for Globally-Asynchronous Locally-Synchronous (GALS) circuits this paper presents two significant enhancements. Fi...
ISLPED
2004
ACM
13 years 10 months ago
2004
ACM
As clock frequency and die area increase, achieving energy efficiency, while distributing a low skew, global clock signal becomes increasingly difficult. Challenges imposed by dee...