Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture

In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architecture has been designed to be used in a Globally Asynchronous Locally Synchronous clusterized Multi Processors System on Chip. The 5 relevant parameters are Silicon Area, Network Saturation Threshold, Communication Throughput, Packet Latency and Power Consumption. Both architectures have been physically implemented and simulated by SystemC/VHDL co-simulation. The electrical parameters have also been evaluated by post layout SPICE simulation for a 90nm CMOS fabrication process, taking into account the long wire effects.

• Type: Conference
• Year: 2007
• Where: DATE
• Authors: Abbas Sheibanyrad, Ivan Miro Panades, Alain Greiner
• Keywords: Asynchronous, DATE 2007, Hardware, Network Saturation Threshold, Synchronous Clusterized Multi