Sciweavers

Share
DATE
2007
IEEE

Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture

9 years 5 months ago
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture
In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architecture has been designed to be used in a Globally Asynchronous Locally Synchronous clusterized Multi Processors System on Chip. The 5 relevant parameters are Silicon Area, Network Saturation Threshold, Communication Throughput, Packet Latency and Power Consumption. Both architectures have been physically implemented and simulated by SystemC/VHDL co-simulation. The electrical parameters have also been evaluated by post layout SPICE simulation for a 90nm CMOS fabrication process, taking into account the long wire effects.
Abbas Sheibanyrad, Ivan Miro Panades, Alain Greine
Added 02 Jun 2010
Updated 02 Jun 2010
Type Conference
Year 2007
Where DATE
Authors Abbas Sheibanyrad, Ivan Miro Panades, Alain Greiner
Comments (0)
books