41 search results - page 2 / 9 » M-trie: an efficient approach to on-chip logic minimization |
ASYNC
2001
IEEE
13 years 9 months ago
2001
IEEE
This paper presents a new approach to two-level hazardfree sum-of-products logic minimization. No currently available minimizers for single-output literal-exact two-level hazard-f...
VLDB
1990
ACM
13 years 9 months ago
1990
ACM
In this paper, we present an efficient algorithm for managing replicated data. We impose a logical tree structure on the set of copies of an object. In a failurefree environment t...
EUSFLAT
2009
13 years 3 months ago
2009
Abstract-- In this paper, we deal with the production and transportation planning of a household appliances manufacturer that has production facilities and central stores for resel...
FPL
2000
Springer
13 years 9 months ago
2000
Springer
Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...