An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis

In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power reduction in PTL circuits to that of BDD decomposition and solve the latter using the max-flow min-cut technique. We use transistor level power estimates to guide the BDD decomposition algorithm. We present the results obtained by running our algorithm on a set of MCNC benchmark circuits, and show on an average of 47% power reduction over these circuits; the comparison with the previously proposed low power pass transistor logic synthesis algorithms shows an average improvement of over 23% over the best previously published approach.

• Type: Conference
• Year: 2002
• Where: VLSID
• Authors: Rupesh S. Shelar, Sachin S. Sapatnekar
• Keywords: Computer Architecture, Pass Transistor Logic, Power Pass Transistor, Transistor Level Power, VLSID 2002