22 search results - page 1 / 5 » MAIA: a framework for networks on chip generation and verifi... |
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
- The increasing complexity of SoCs makes networks on chip (NoC) a promising substitute for busses and dedicated wires interconnection schemes. However, new tools need to be develo...
DAC
2003
ACM
14 years 5 months ago
2003
ACM
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
ICSE
2009
IEEE-ACM
13 years 2 months ago
2009
IEEE-ACM
Verifying security properties of protocols requires developers to manually create protocol-specific intruder models, which could be tedious and error prone. We present Slede, a ve...
SBCCI
2005
ACM
13 years 10 months ago
2005
ACM
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
PERCOM
2007
ACM
14 years 4 months ago
2007
ACM
Pervasive computing applications are tedious to develop because they combine a number of problems ranging from device heterogeneity, to middleware constraints, to lack of programm...