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ASPDAC
2009
ACM
249views Hardware» more  ASPDAC 2009»
13 years 9 months ago
Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model
— This paper proposes the first automatic approach to simultaneously generate Cycle Accurate and Cycle Count Accurate transaction level bus models. Since TLM (Transaction Level M...
Chen Kang Lo, Ren-Song Tsay
VLSID
2006
IEEE
192views VLSI» more  VLSID 2006»
13 years 10 months ago
Beyond RTL: Advanced Digital System Design
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
Shiv Tasker, Rishiyur S. Nikhil
HPCN
1998
Springer
13 years 8 months ago
The GRED Graphical Editor for the GRADE Parallel Program Development Environment
In this paper, we describe a graphical editor GRED as part of the integrated programming environment GRADE that is intended to support designing, debugging and performance tuning o...
Péter Kacsuk, Gábor Dózsa, Ti...
MSE
2005
IEEE
148views Hardware» more  MSE 2005»
13 years 10 months ago
Teaching System-Level Design Using SpecC and SystemC
System-level design of embedded computer systems is essential to manage complexity and enhance designer productivity. Viewing designs at t abstraction levels allows developers to ...
Robert D. Walstrom, Joseph Schneider, Diane T. Rov...
IJHPCA
2007
114views more  IJHPCA 2007»
13 years 4 months ago
An Approach To Data Distributions in Chapel
A key characteristic of today’s high performance computing systems is a physically distributed memory, which makes the efficient management of locality essential for taking adv...
R. E. Diaconescu, Hans P. Zima