85 search results - page 17 / 17 » Mapping Interconnection Networks into VEDIC Networks |
FCCM
2006
IEEE
13 years 11 months ago
2006
IEEE
— Many important applications are organized around long-lived, irregular sparse graphs (e.g., data and knowledge bases, CAD optimization, numerical problems, simulations). The gr...
ISLPED
2005
ACM
13 years 11 months ago
2005
ACM
In this paper, we take the idea of application-level processing on disks to one level further, and focus on an architecture, called Cluster of Active Disks (CAD), where the storag...
ERSA
2006
13 years 7 months ago
2006
Reconfigurable supercomputing (RSC) combines programmable logic chips with high performance microprocessors, all communicating over a high bandwidth, low latency interconnection n...
JSA
2007
13 years 5 months ago
2007
Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications. To enable MP-SoC platforms, scalable communication-centric inter...
PARA
2000
Springer
13 years 9 months ago
2000
Springer
Our proposal has the following key features: 1) The separation of a distributed program into a pure algorithm (PurAl) and a distribution/communication declaration (DUAL). This yie...