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ISVLSI
2002
IEEE
109views VLSI» more  ISVLSI 2002»
13 years 10 months ago
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnn...
ESANN
2006
13 years 6 months ago
Parallel hardware implementation of a broad class of spiking neurons using serial arithmetic
Abstract. Current digital, directly mapped implementations of spiking neural networks use serial processing and parallel arithmetic. On a standard CPU, this might be the good choic...
Benjamin Schrauwen, Jan M. Van Campenhout
DEXAW
2007
IEEE
172views Database» more  DEXAW 2007»
13 years 9 months ago
X-SOM: A Flexible Ontology Mapper
System interoperability is a well known issue, especially for heterogeneous information systems, where ontologybased representations may support automatic and usertransparent inte...
Carlo Curino, Giorgio Orsi, Letizia Tanca
TVLSI
1998
88views more  TVLSI 1998»
13 years 5 months ago
Time multiplexed color image processing based on a CNN with cell-state outputs
—A practical system approach for time-multiplexing cellular neural network (CNN) implementations suitable for processing large and complex images using small CNN arrays is presen...
Lei Wang, José Pineda de Gyvez, Edgar S&aac...
ASPDAC
2004
ACM
96views Hardware» more  ASPDAC 2004»
13 years 9 months ago
Rate analysis for streaming applications with on-chip buffer constraints
While mapping a streaming (such as multimedia or network packet processing) application onto a specified architecture, an important issue is to determine the input stream rates tha...
Alexander Maxiaguine, Simon Künzli, Samarjit ...