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» Massively Parallel Architectures and Polymer Simulation
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CF
2007
ACM
13 years 9 months ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
ISCAS
2003
IEEE
103views Hardware» more  ISCAS 2003»
13 years 10 months ago
A massively scaleable decoder architecture for low-density parity-check codes
A massively scalable architecture for decoding low-density parity-check codes is presented in this paper. This novel architecture uses hardware scaling and memory partitioning to ...
Anand Selvarathinam, Gwan Choi, Krishna Narayanan,...
IEEEHPCS
2010
13 years 3 months ago
Scalable instruction set simulator for thousand-core architectures running on GPGPUs
Simulators are still the primary tools for development and performance evaluation of applications running on massively parallel architectures. However, current virtual platforms a...
Shivani Raghav, Martino Ruggiero, David Atienza, C...
ICPR
2004
IEEE
14 years 6 months ago
From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers
Parallel processors such as SIMD computers have been successfully used in various areas of high performance image and data processing. Due to their characteristics of highly regula...
Jie Han, Pieter Jonker
IPPS
2005
IEEE
13 years 11 months ago
Data Redistribution and Remote Method Invocation in Parallel Component Architectures
With the increasing availability of high-performance massively parallel computer systems, the prevalence of sophisticated scientific simulation has grown rapidly. The complexity ...
Felipe Bertrand, Randall Bramley, Alan Sussman, Da...