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CF
2007
ACM
13 years 9 months ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
ACSD
2009
IEEE
139views Hardware» more  ACSD 2009»
14 years 8 days ago
Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million Processors
The SpiNNaker project aims to develop parallel computer systems with more than a million embedded processors. The goal of the project is to support largescale simulations of syste...
Stephen B. Furber, Andrew D. Brown
MVA
1992
101views Computer Vision» more  MVA 1992»
13 years 6 months ago
Contour Based Image Segmentation Process on a Parallel Vision Machine
Image processing applications need shorter processing times. This requires the parallelization of low and mid levels sequential process chains on specific machines. In this paper ...
Pascal Legrand, Jean-Pierre Dérutin
IPPS
1998
IEEE
13 years 9 months ago
A Parallel Algorithm for Minimum Cost Path Computation on Polymorphic Processor Array
This paper describes a new parallel algorithm for Minimum Cost Path computation on the Polymorphic Processor Array, a massively parallel architecture based on a reconfigurable mesh...
Pierpaolo Baglietto, Massimo Maresca, Mauro Miglia...
ICPP
1993
IEEE
13 years 9 months ago
Data-Parallel R-Tree Algorithms
Abstract Data-parallel algorithms for R-trees, a common spatial data structure are presented, in the domain of planar line segment data e.g., Bureau of the Census TIGER Line les....
Erik G. Hoel, Hanan Samet