39 search results - page 4 / 8 » Matrix Multiplication on Two Interconnected Processors |
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
ICCS
2001
Springer
13 years 10 months ago
2001
Springer
Abstract. Sparse matrix-vector multiplication is an important computational kernel that tends to perform poorly on modern processors, largely because of its high ratio of memory op...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
ICPPW
2002
IEEE
13 years 10 months ago
2002
IEEE
In this paper, we use the tensor product notation as the framework of a programming methodology for designing block recursive algorithms on various computer networks. In our previ...