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» Maximizing Multiprocessor Performance with the SUIF Compiler
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DTJ
1998
44views more  DTJ 1998»
13 years 4 months ago
Maximizing Multiprocessor Performance with the SUIF Compiler
Mary W. Hall, Jennifer-Ann M. Anderson, Saman P. A...
LCTRTS
2010
Springer
13 years 2 months ago
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin,...
DAC
2007
ACM
14 years 5 months ago
Program Mapping onto Network Processors by Recursive Bipartitioning and Refining
Mapping packet processing applications onto embedded network processors (NP) is a challenging task due to the unique constraints of NP systems and the characteristics of network a...
Jia Yu, Jingnan Yao, Jun Yang 0002, Laxmi N. Bhuya...
CASES
2009
ACM
13 years 11 months ago
Optimal loop parallelization for maximizing iteration-level parallelism
This paper solves the open problem of extracting the maximal number of iterations from a loop that can be executed in parallel on chip multiprocessors. Our algorithm solves it opt...
Duo Liu, Zili Shao, Meng Wang, Minyi Guo, Jingling...
ICPP
1998
IEEE
13 years 9 months ago
A memory-layout oriented run-time technique for locality optimization
Exploiting locality at run-time is a complementary approach to a compiler approach for those applications with dynamic memory access patterns. This paper proposes a memory-layout ...
Yong Yan, Xiaodong Zhang, Zhao Zhang