26 search results - page 2 / 6 » Maximizing Performance by Retiming and Clock Skew Scheduling |
ICCAD
2009
IEEE
13 years 3 months ago
2009
IEEE
Clock skew scheduling has been effectively used to reduce the clock period of sequential circuits. However, this technique may become impractical if a different skew must be appli...
DATE
2006
IEEE
14 years 6 days ago
2006
IEEE
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
ICCAD
2004
IEEE
14 years 3 months ago
2004
IEEE
Traditional timing-driven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. As a result, the ...
DAC
1996
ACM
13 years 10 months ago
1996
ACM
1- A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This met...
DATE
2009
IEEE
14 years 28 days ago
2009
IEEE
Multi-domain clock skew scheduling is a cost effective technique for performance improvement. However, the required wire length and area overhead due to phase shifters for realizin...