35 search results - page 1 / 7 » Maximum Current Estimation in Programmable Logic Arrays |
GLVLSI
1998
IEEE
13 years 9 months ago
1998
IEEE
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Power gating is emerging as a viable solution to reduction of leakage current. However, power gated circuits are different from the conventional designs in the sense that a power-...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...
ISSS
2002
IEEE
13 years 10 months ago
2002
IEEE
We propose a high-level analytical model for estimating the energy and/or power dissipation in VLSI processor (systolic) array implementations of loop programs, particularly for i...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...