753 search results - page 150 / 151 » Mechanisms for Mapping High-Level Parallel Performance Data |
APVIS
2007
13 years 7 months ago
2007
: In this paper, we apply Particle-based Volume Rendering (PBVR) technique using a current programmable GPU architecture. Recently, the increasing programmability of GPU offers an ...
BIOINFORMATICS
2010
13 years 5 months ago
2010
Motivation: The fruit fly (Drosophila melanogaster) is a commonly used model organism in biology. We are currently building a 3D digital atlas of the fruit fly larval nervous syst...
ICS
2003
Tsinghua U.
13 years 11 months ago
2003
Tsinghua U.
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture ass...
DSN
2011
IEEE
12 years 5 months ago
2011
IEEE
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
SIGMOD
2009
ACM
14 years 6 months ago
2009
ACM
The query models of the recent generation of very large scale distributed (VLSD) shared-nothing data storage systems, including our own PNUTS and others (e.g. BigTable, Dynamo, Ca...