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» Mechanisms for Mapping High-Level Parallel Performance Data
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IPCCC
2006
IEEE
13 years 11 months ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John
TPDS
1998
129views more  TPDS 1998»
13 years 4 months ago
The Offset Cube: A Three-Dimensional Multicomputer Network Topology Using Through-Wafer Optics
—Three-dimensional packaging technologies are critical for enabling ultra-compact, massively parallel processors (MPPs) for embedded applications. Through-wafer optical interconn...
W. Stephen Lacy, José Cruz-Rivera, D. Scott...

Publication
232views
13 years 3 months ago
Measurement in 802.11 Wireless Networks and its Applications
Ease of deployment, wireless connectivity and ubiquitous mobile on-the-go computing has made the IEEE 802.11 the most widely deployed Wireless Local Area Network (WLAN) sta...
Malik Ahmad Yar Khan