206 search results - page 2 / 42 » Mechanisms for store-wait-free multiprocessors |
CAL
2006
13 years 5 months ago
2006
This paper evaluates asymmetric cluster chip multiprocessor (ACCMP) architectures as a mechanism to achieve the highest performance for a given power budget. ACCMPs execute serial ...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
— We present a novel hardware mechanism for dynamic program phase detection in distributed sharedmemory (DSM) multiprocessors. We show that successful hardware mechanisms for pha...
ISCA
1998
IEEE
13 years 9 months ago
1998
IEEE
The design challenge for large-scale multiprocessors is (1) to minimize communication overhead, (2) allow communication to overlap computation, and (3) coordinate the two without ...
HASE
1997
IEEE
13 years 9 months ago
1997
IEEE
Abstract: We present a time-bounded state-based communication mechanism for dynamically reconfigurable embedded systems. The mechanism is a single-processor, low-overhead version o...
SUTC
2008
IEEE
13 years 11 months ago
2008
IEEE
In this paper, we address the power-aware scheduling of sporadic constrained-deadline hard real-time tasks using dynamic voltage scaling upon multiprocessor platforms. We propose ...