206 search results - page 3 / 42 » Mechanisms for store-wait-free multiprocessors |
ARCS
2006
Springer
13 years 9 months ago
2006
Springer
Abstract. This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors (CMP) and its corresponding pre-layout simulation results usin...
IPPS
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper presents a new approach to improve performance of Java programs by extending the superthreaded speculative execution model [14, 15] to exploit coarsegrained parallelism...
ISCA
2006
IEEE
13 years 11 months ago
2006
IEEE
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
To maintain coherence in conventional shared-memory multiprocessor systems, processors first check other processors’ caches before obtaining data from memory. This coherence che...
ARCS
1997
Springer
13 years 9 months ago
1997
Springer
To provide a computing system to be dependable fault tolerance mechanisms have to be included. Especially massive parallelism represents a new challenge for fault tolerance. In th...