206 search results - page 4 / 42 » Mechanisms for store-wait-free multiprocessors |
VLSID
2006
IEEE
14 years 1 days ago
2006
IEEE
This paper presents Frame Based Fair Multiprocessor Scheduler (FBFMS) which provides accurate real-time proportional fair scheduling for a set of dynamic tasks on a symmetric mult...
JSA
2007
13 years 6 months ago
2007
This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors (CMP) and its corresponding pre-layout simulation results using VHDL. T...
HPCA
1995
IEEE
13 years 9 months ago
1995
IEEE
Shared memory is an appealing abstraction for parallel programming. It must be implemented with caches in order toperform well, however, and caches require a coherence mechanism t...
MICRO
2008
IEEE
14 years 13 days ago
2008
IEEE
Higher level of resource integration and the addition of new features in modern multi-processors put a significant pressure on their verification. Although a large amount of res...
TC
1998
13 years 5 months ago
1998
—We evaluate three extensions to directory-based cache coherence protocols in shared-memory multiprocessors. These extensions are aimed at reducing the penalties associated with ...