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» Memory Access Schemes for Configurable Processors
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ISCA
2008
IEEE
148views Hardware» more  ISCA 2008»
14 years 1 days ago
Atomic Vector Operations on Chip Multiprocessors
The current trend is for processors to deliver dramatic improvements in parallel performance while only modestly improving serial performance. Parallel performance is harvested th...
Sanjeev Kumar, Daehyun Kim, Mikhail Smelyanskiy, Y...
DATE
2006
IEEE
114views Hardware» more  DATE 2006»
13 years 9 months ago
Compositional, efficient caches for a chip multi-processor
In current multi-media systems major parts of the functionality consist of software tasks executed on a set of concurrently operating processors. Those tasks interfere with each o...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
ISCA
2006
IEEE
182views Hardware» more  ISCA 2006»
13 years 11 months ago
Cooperative Caching for Chip Multiprocessors
This paper presents CMP Cooperative Caching, a unified framework to manage a CMP’s aggregate on-chip cache resources. Cooperative caching combines the strengths of private and ...
Jichuan Chang, Gurindar S. Sohi
TVLSI
2008
139views more  TVLSI 2008»
13 years 5 months ago
Ternary CAM Power and Delay Model: Extensions and Uses
Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search...
Banit Agrawal, Timothy Sherwood
DAC
2006
ACM
14 years 6 months ago
High-level power management of embedded systems with application-specific energy cost functions
Most existing dynamic voltage scaling (DVS) schemes for multiple tasks assume an energy cost function (energy consumption versus execution time) that is independent of the task ch...
Youngjin Cho, Naehyuck Chang, Chaitali Chakrabarti...