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» Memory Access Schemes for Configurable Processors
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HPCA
1995
IEEE
13 years 8 months ago
Access Ordering and Memory-Conscious Cache Utilization
As processor speeds increase relative to memory speeds, memory bandwidth is rapidly becoming the limiting performance factor for many applications. Several approaches to bridging ...
Sally A. McKee, William A. Wulf
DDECS
2006
IEEE
95views Hardware» more  DDECS 2006»
13 years 11 months ago
Parallel Memory Architecture for Arbitrary Stride Accesses
—Parallel memory modules can be used to increase memory bandwidth and feed a processor with only necessary data. Arbitrary stride access capability with interleaved memories is d...
Eero Aho, Jarno Vanne, Timo D. Hämäl&aum...
IPPS
2009
IEEE
13 years 11 months ago
Core-aware memory access scheduling schemes
Multi-core processors have changed the conventional hardware structure and require a rethinking of system scheduling and resource management to utilize them efficiently. However, ...
Zhibin Fang, Xian-He Sun, Yong Chen, Surendra Byna
HPCA
2000
IEEE
13 years 9 months ago
Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors
We consider a variety of dynamic, hardware-based methods for exploiting load/store parallelism, including mechanisms that use memory dependence speculation. While previous work ha...
Andreas Moshovos, Gurindar S. Sohi
MVA
1992
143views Computer Vision» more  MVA 1992»
13 years 6 months ago
A Real-Time Vision System Using Integrated Memory Array Processor Prototype LSI
This study reports on the performance of a Real-Time Vision System (RVS) and its use of an IMAP prototype LSI. This LSI integrates eight 8 bit processors and a 144 Kbit SRAM on a ...
Yoshihiro Fujita, Nobuyuki Yamashita, Shin'ichiro ...