741 search results - page 1 / 149 » Memory Dependence Prediction Using Store Sets |
ISCA
1998
IEEE
13 years 9 months ago
1998
IEEE
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that wri...
IEEEPACT
2002
IEEE
13 years 10 months ago
2002
IEEE
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruction level parallelism by issuing load instructions at the earliest time withou...
HPCA
2006
IEEE
14 years 5 months ago
2006
IEEE
Allowing loads to issue out-of-order with respect to earlier unresolved store addresses is very important for extracting parallelism in large-window superscalar processors. Blindl...
JILP
2000
13 years 5 months ago
2000
We identify that a set of multimedia applications exhibit highly regular read-after-read (RAR) and read-after-write (RAW) memory dependence streams. We exploit this regularity to ...
ICS
1999
Tsinghua U.
13 years 9 months ago
1999
Tsinghua U.
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...