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» Memory Estimation for High Level Synthesis
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EH
2004
IEEE
117views Hardware» more  EH 2004»
13 years 9 months ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
ASAP
2009
IEEE
141views Hardware» more  ASAP 2009»
14 years 2 months ago
Accelerating a Virtual Ecology Model with FPGAs
—This paper describes the acceleration of virtual ecology models using field-programmable gate arrays (FPGAs). Our approach targets models generated by the Virtual Ecology Workb...
Julien Lamoureux, Tony Field, Wayne Luk
ISCA
2011
IEEE
386views Hardware» more  ISCA 2011»
12 years 9 months ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...
NIPS
2004
13 years 6 months ago
Probabilistic Inference of Alternative Splicing Events in Microarray Data
Alternative splicing (AS) is an important and frequent step in mammalian gene expression that allows a single gene to specify multiple products, and is crucial for the regulation ...
Ofer Shai, Brendan J. Frey, Quaid Morris, Qun Pan,...
BMCBI
2005
62views more  BMCBI 2005»
13 years 5 months ago
Differences in codon bias cannot explain differences in translational power among microbes
Background: Translational power is the cellular rate of protein synthesis normalized to the biomass invested in translational machinery. Published data suggest a previously unreco...
Les Dethlefsen, Thomas M. Schmidt