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LCTRTS
2010
Springer
13 years 11 months ago
Versatile system-level memory-aware platform description approach for embedded MPSoCs
In this paper, we present a novel system modeling language which targets primarily the development of source-level multiprocessor memory aware optimizations. In contrast to previo...
Robert Pyka, Felipe Klein, Peter Marwedel, Stylian...
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
13 years 10 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
CAL
2007
13 years 4 months ago
A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed memory hierarchy enhancements for coher...
Jason Zebchuk, Andreas Moshovos
WSC
2001
13 years 6 months ago
Use of DaSSF in a scalable multiprocessor wireless simulation architecture
The problem of efficient load distribution and scaling of large-scale wireless communication system simulation on multiprocessor architectures (both shared memory and cluster arra...
Trefor J. Delve, Nathan Smith
CODES
2006
IEEE
13 years 10 months ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt