Sciweavers

87 search results - page 2 / 18
» Memory Management in a Combined VIA SCI Hardware
Sort
View
INTEGRATION
2000
71views more  INTEGRATION 2000»
13 years 4 months ago
A hardware implementation of realloc function
The memory intensive nature of object-oriented languages such as C++ and Java has created the need of a high-performance dynamic memory management. Objectoriented applications oft...
Witawas Srisa-an, Chia-Tien Dan Lo, J. Morris Chan...
SC
1995
ACM
13 years 8 months ago
A Performance Evaluation of the Convex SPP-1000 Scalable Shared Memory Parallel Computer
The Convex SPP-1000 is the first commercial implementation of a new generation of scalable shared memory parallel computers with full cache coherence. It employs a hierarchical s...
Thomas L. Sterling, Daniel Savarese, Peter MacNeic...
ISCA
1998
IEEE
145views Hardware» more  ISCA 1998»
13 years 9 months ago
Multi-Level Texture Caching for 3D Graphics Hardware
Traditional graphics hardware architectures implement what we call the push architecture for texture mapping. Local memory is dedicated to the accelerator for fast local retrieval...
Michael Cox, Narendra Bhandri, Michael Shantz
DATE
2002
IEEE
94views Hardware» more  DATE 2002»
13 years 9 months ago
A Powerful System Design Methodology Combining OCAPI and Handel-C for Concept Engineering
In this paper, we present an efficient methodology to validate high performance algorithms and prototype them using reconfigurable hardware. We follow a strict topdown Hardware/So...
Klaus Buchenrieder, Andreas Pyttel, Alexander Sedl...
AICCSA
2006
IEEE
102views Hardware» more  AICCSA 2006»
13 years 8 months ago
An Experimental and Industrial Experience: Avoiding Denial of Service via Memory Profiling
Poor memory management leads to memory leaks, which cause significant performance degradation and failure of software. If ignored, such leaks can potentially cause security breach...
Saeed Abu-Nimeh, Suku Nair, Marco F. Marchetti