34 search results - page 1 / 7 » Memory Model = Instruction Reordering Store Atomicity |
ISCA
2006
IEEE
13 years 11 months ago
2006
IEEE
We present a novel framework for defining memory models in terms of two properties: thread-local Instruction Reordering axioms and Store Atomicity, which describes inter-thread c...
HPCA
2005
IEEE
14 years 5 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
CAV
2009
Springer
14 years 5 months ago
2009
Springer
Abstract. Pseudo-code descriptions of STMs assume sequentially consistent program execution and atomicity of high-level STM operations like read, write, and commit. These assumptio...
CGO
2009
IEEE
13 years 11 months ago
2009
IEEE
—Most research into high-performance software transactional memory (STM) assumes that transactions will run on a processor with a relatively strict memory model, such as Total St...
CAV
2010
Springer
13 years 8 months ago
2010
Springer
We present a class of relaxed memory models, defined in Coq, parameterised by the chosen permitted local reorderings of reads and writes, and the visibility of inter- and intra-pr...