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2009
IEEE

Reducing Memory Ordering Overheads in Software Transactional Memory

10 years 6 months ago
Reducing Memory Ordering Overheads in Software Transactional Memory
—Most research into high-performance software transactional memory (STM) assumes that transactions will run on a processor with a relatively strict memory model, such as Total Store Ordering (TSO). To execute these algorithms correctly on processors with relaxed memory models, explicit fence instructions may be required on every transactional access, and neither the processor nor the compiler may be able to safely reorder transactional reads. The overheads of fence instructions and read serialization are a significant but unstudied source of latency for STM, with impact on the tradeoffs among different STM systems and on the optimizations that may be possible for any given system. Straightforward ports of STM runtimes from strict to relaxed machines may fail to realize the latter’s performance potential. We explore the implementation of STM for machines with relaxed memory consistency using two recent high-performance STM systems. We propose compiler optimizations that can safely ...
Michael F. Spear, Maged M. Michael, Michael L. Sco
Added 18 May 2010
Updated 18 May 2010
Type Conference
Year 2009
Where CGO
Authors Michael F. Spear, Maged M. Michael, Michael L. Scott, Peng Wu
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