34 search results - page 7 / 7 » Memory Model = Instruction Reordering Store Atomicity |
IPPS
2002
IEEE
13 years 10 months ago
2002
IEEE
In a paper presented last year at WMPP’01 [Walker01], we described the initial prototype of an associative processor implemented using field-programmable logic devices (FPLDs). ...
VISUALIZATION
2005
IEEE
13 years 11 months ago
2005
IEEE
Recent years have seen an immense increase in the complexity of geometric data sets. Today’s gigabyte-sized polygon models can no longer be completely loaded into the main memor...
MICRO
2010
IEEE
13 years 4 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
ESEC
1999
Springer
13 years 10 months ago
1999
Springer
The use of smart cards to run software modules on demand has become a major business concern for application issuers. Such downloadable executable content requires to be trusted by...