16 search results - page 1 / 4 » Memory Modeling in ESL-RTL Equivalence Checking |
DAC
2007
ACM
13 years 8 months ago
2007
ACM
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
C++ based verification methodologies are now emerging as the preferred method for SOC design. However most of the verification involving the C++ models are simulation based. The c...
CONCUR
2008
Springer
13 years 6 months ago
2008
Springer
Software transactional memory (STM) offers a disciplined concurrent programming model for exploiting the parallelism of modern processor architectures. This paper presents the firs...
CAV
2006
Springer
13 years 8 months ago
2006
Springer
Many multithreaded programs employ concurrent data types to safely share data among threads. However, highly-concurrent algorithms for even seemingly simple data types are difficul...
VLSID
2001
IEEE
14 years 5 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...