Sciweavers

16 search results - page 1 / 4
» Memory Modeling in ESL-RTL Equivalence Checking
Sort
View
DAC
2007
ACM
14 years 2 months ago
Memory Modeling in ESL-RTL Equivalence Checking
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
Alfred Kölbl, Jerry R. Burch, Carl Pixley
DAC
2008
ACM
14 years 11 months ago
Construction of concrete verification models from C++
C++ based verification methodologies are now emerging as the preferred method for SOC design. However most of the verification involving the C++ models are simulation based. The c...
Malay Haldar, Gagandeep Singh, Saurabh Prabhakar, ...
CONCUR
2008
Springer
14 years 16 days ago
Completeness and Nondeterminism in Model Checking Transactional Memories
Software transactional memory (STM) offers a disciplined concurrent programming model for exploiting the parallelism of modern processor architectures. This paper presents the firs...
Rachid Guerraoui, Thomas A. Henzinger, Vasu Singh
CAV
2006
Springer
165views Hardware» more  CAV 2006»
14 years 2 months ago
Bounded Model Checking of Concurrent Data Types on Relaxed Memory Models: A Case Study
Many multithreaded programs employ concurrent data types to safely share data among threads. However, highly-concurrent algorithms for even seemingly simple data types are difficul...
Sebastian Burckhardt, Rajeev Alur, Milo M. K. Mart...
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
14 years 11 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann