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ENTCS
2007
99views more  ENTCS 2007»
13 years 10 months ago
Extending Symmetry Reduction Techniques to a Realistic Model of Computation
Much of the literature on symmetry reductions for model checking assumes a simple model of computation where the local state of each component in a concurrent system can be repres...
Alastair F. Donaldson, Alice Miller
DSD
2004
IEEE
129views Hardware» more  DSD 2004»
14 years 2 months ago
Functional Validation of Programmable Architectures
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
Prabhat Mishra, Nikil D. Dutt
DAC
1996
ACM
14 years 2 months ago
Integrating Formal Verification Methods with A Conventional Project Design Flow
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
Ásgeir Th. Eiríksson
VLSID
2003
IEEE
180views VLSI» more  VLSID 2003»
14 years 11 months ago
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
Pao-Ann Hsiung, Shu-Yu Cheng
PPOPP
2009
ACM
14 years 11 months ago
Formal verification of practical MPI programs
This paper considers the problem of formal verification of MPI programs operating under a fixed test harness for safety properties without building verification models. In our app...
Anh Vo, Sarvani S. Vakkalanka, Michael Delisi, Gan...