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» Memory Usage Verification Using Hip Sleek
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ATVA
2009
Springer
97views Hardware» more  ATVA 2009»
13 years 5 months ago
Memory Usage Verification Using Hip/Sleek
Embedded systems often come with constrained memory footprints. It is therefore essential to ensure that software running on such platforms fulfils memory usage specifications at c...
Guanhua He, Shengchao Qin, Chenguang Luo, Wei-Ngan...
AINA
2008
IEEE
13 years 11 months ago
Performance Optimization of Temporal Reasoning for Grid Workflows Using Relaxed Region Analysis
With quick evolution of grid technologies and increasing complexity of e-Science applications, reasoning temporal properties of grid workflows to ensure reliability and trustworth...
Ke Xu, Junwei Cao, Lianchen Liu, Cheng Wu
CAV
1998
Springer
98views Hardware» more  CAV 1998»
13 years 9 months ago
Verification of Timed Systems Using POSETs
This paper presents a new algorithm for efficiently verifying timed systems. The new algorithm represents timing information using geometric regions and explores the timed state sp...
Wendy Belluomini, Chris J. Myers
IWMM
2010
Springer
140views Hardware» more  IWMM 2010»
13 years 6 months ago
Parametric inference of memory requirements for garbage collected languages
The accurate prediction of program's memory requirements is a critical component in software development. Existing heap space analyses either do not take deallocation into ac...
Elvira Albert, Samir Genaim, Miguel Gómez-Z...
DAC
2006
ACM
14 years 5 months ago
Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
Xiushan Feng, Alan J. Hu