2 search results - page 1 / 1 » Memory mapped ECC: low-cost error protection for last level ... |
ISCA
2009
IEEE
14 years 2 days ago
2009
IEEE
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
SIGMETRICS
2011
ACM
12 years 8 months ago
2011
ACM
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches d...