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DATE
2000
IEEE
130views Hardware» more  DATE 2000»
13 years 10 months ago
Optimal Hardware Pattern Generation for Functional BIST
∗∗ Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses t...
Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, H...
ISCAS
1999
IEEE
106views Hardware» more  ISCAS 1999»
13 years 10 months ago
Test pattern generation for width compression in BIST
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...
Paulo F. Flores, Horácio C. Neto, K. Chakra...
BMCBI
2004
196views more  BMCBI 2004»
13 years 5 months ago
MUSCLE: a multiple sequence alignment method with reduced time and space complexity
Background: In a previous paper, we introduced MUSCLE, a new program for creating multiple alignments of protein sequences, giving a brief summary of the algorithm and showing MUS...
Robert C. Edgar
ITC
2000
IEEE
84views Hardware» more  ITC 2000»
13 years 9 months ago
Non-intrusive BIST for systems-on-a-chip
1 The term "functional BIST" describes a test method to control functional modules so that they generate a deterministic test set, which targets structural faults within ...
Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wund...
VLSID
2002
IEEE
115views VLSI» more  VLSID 2002»
14 years 6 months ago
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits
We describe a built-in test pattern generation method for scan circuits. The method is based on partitioning and storage of test sets. Under this method, a precomputed test set is...
Irith Pomeranz, Sudhakar M. Reddy