15 search results - page 2 / 3 » Microarchitectural power modeling techniques for deep sub-mi... |
IEEEPACT
2002
IEEE
13 years 9 months ago
2002
IEEE
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we inv...
MTV
2006
IEEE
13 years 10 months ago
2006
IEEE
Simulation-based validation of the current industrial processors typically use huge number of test programs generated at instruction set architecture (ISA) level. However, archite...
MICRO
2007
IEEE
13 years 11 months ago
2007
IEEE
Program runtime characteristics exhibit significant variation. As microprocessor architectures become more complex, their efficiency depends on the capability of adapting with wor...
MICRO
2008
IEEE
13 years 11 months ago
2008
IEEE
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
ISSS
1995
IEEE
13 years 8 months ago
1995
IEEE
This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been dev...