48 search results - page 9 / 10 » Minimizing the embedding impact in steganography |
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prio...
RTAS
2005
IEEE
13 years 11 months ago
2005
IEEE
We consider the problem of energy minimization for periodic preemptive hard real-time tasks that are scheduled on an identical multiprocessor platform with dynamic voltage scaling...
RTSS
2003
IEEE
13 years 11 months ago
2003
IEEE
This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units and out-oforder ex...
TCAD
2002
13 years 5 months ago
2002
Specialized clustered very large instruction word (VLIW) processors combined with effective compilation techniques enable aggressive exploitation of the high instruction-level para...
FPGA
2005
ACM
13 years 11 months ago
2005
ACM
Recent works demonstrate several benefits of synthesizing software binaries onto FPGA hardware, including incorporating hardware design into established software tool flows with m...