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» Miss Rate Prediction across All Program Inputs
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CASES
2010
ACM
13 years 3 months ago
Improved procedure placement for set associative caches
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...
Yun Liang, Tulika Mitra
IEEEPACT
2009
IEEE
14 years 12 days ago
Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level Partitioning
—Performance degradation of memory-intensive programs caused by the LRU policy’s inability to handle weaklocality data accesses in the last level cache is increasingly serious ...
Qingda Lu, Jiang Lin, Xiaoning Ding, Zhao Zhang, X...
PPPJ
2009
ACM
13 years 10 months ago
Virtual reuse distance analysis of SPECjvm2008 data locality
Reuse distance analysis has been proved promising in evaluating and predicting data locality for programs written in Fortran or C/C++. But its effect has not been examined for ap...
Xiaoming Gu, Xiao-Feng Li, Buqi Cheng, Eric Huang
DAC
2010
ACM
13 years 6 months ago
Instruction cache locking using temporal reuse profile
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
Yun Liang, Tulika Mitra
PPOPP
2005
ACM
13 years 11 months ago
Exposing disk layout to compiler for reducing energy consumption of parallel disk based systems
Disk subsystem is known to be a major contributor to overall power consumption of high-end parallel systems. Past research proposed several architectural level techniques to reduc...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir, A...